If we have only a single active pipe and the cdclk change only requires
the cd2x divider to be updated bxt+ can do the update with forcing a full
modeset on the pipe. Try to hook that up.
v2:
- Wait for vblank after an optimized CDCLK change.
- Avoid optimization if the pipe needs a modeset (or was disabled).
- Split CDCLK change to a pre/post plane update step.
v3:
- Use correct version of CDCLK state as old state. (Ville)
- Remove unused intel_cdclk_can_skip_modeset()
v4:
- For consistency call intel_set_cdclk_post_plane_update() only during
modesets (and not fastsets).
v5:
- Remove the logic to update the CD2X divider on-the-fly on ICL, since
only a divider of 1 is supported there. Clint also noticed that the
pipe select bits in CDCLK_CTL are oddly defined on ICL, it's not clear
yet whether that's only an error in the specification.
Signed-off-by: Ville Syrjälä <email address hidden>
Signed-off-by: Abhay Kumar <email address hidden>
Tested-by: Abhay Kumar <email address hidden>
Signed-off-by: Imre Deak <email address hidden>
Reviewed-by: Clint Taylor <email address hidden>
Link: https://patchwork<email address hidden>
(backported from commit 59f9e9cab3a1e6762fb707d0d829b982930f1349)
Signed-off-by: Hui Wang <email address hidden>
Signed-off-by: AceLan Kao <email address hidden>
