Don't assume we can get a relative path by cutting of certain prefixes,
since this isn't guaranteed to work.
Instead use a library function.
Also normalize paths in order to take care of symlinks.
If a return address is zero, the script will pass -1 to addr2line which
it considers an invalid flag.
Zero is an unlikely return address, but we might see it, for example
because the backtrace is unreliable on s390x if there is an interrupt
frame on the stack.
- Fix goofs in the configuration related to the new FEP access testcases
- Add a FEP test for an CPL>DPL non-conforming segment load
- Fix issues with the RDPID testcase in the "tsc" test
- Fix various assembler warnings
- Add x2APIC testcases to the "msr" test
- Add PRED_CMD and FLUSH_CMD testscases to the "msr" test
5cf6a3f...
by
Sean Christopherson <email address hidden>
x86/msr: Add testcases for MSR_IA32_FLUSH_CMD and its L1D_FLUSH command
Add test coverage to verify MSR_IA32_FLUSH_CMD is write-only, that it can
be written with '0' (nop command) and '1' (L1D flush command) when the L1D
flush command is suported, and that writing any other bit (1-63) triggers
a #GP due to the bits/commands being reserved.
Signed-off-by: Sean Christopherson <email address hidden>
Signed-off-by: Paolo Bonzini <email address hidden>
Message-Id: <email address hidden>
Signed-off-by: Paolo Bonzini <email address hidden>
fbd9808...
by
Sean Christopherson <email address hidden>
x86/msr: Add testcases for MSR_IA32_PRED_CMD and its IBPB command
Add test coverage to verify MSR_IA32_PRED_CMD is write-only, that it can
be written with '0' (nop command) and '1' (IBPB command) when IBPB is
supported by the CPU (SPEC_CTRL on Intel, IBPB on AMD). Do not check
that writing any other bit (1-63) triggers a #GP due to the bits/commands
being reserved, because some versions of the microcode do not do that.
Signed-off-by: Sean Christopherson <email address hidden>
Signed-off-by: Paolo Bonzini <email address hidden>
Message-Id: <email address hidden>
Signed-off-by: Paolo Bonzini <email address hidden>
4fba1a2...
by
Sean Christopherson <email address hidden>
x86: Add define for MSR_IA32_PRED_CMD's PRED_CMD_IBPB (bit 0)
Add a define for PRED_CMD_IBPB and use it to replace the open coded '1' in
the nVMX library.
Signed-off-by: Sean Christopherson <email address hidden>
Signed-off-by: Paolo Bonzini <email address hidden>
Message-Id: <email address hidden>
Signed-off-by: Paolo Bonzini <email address hidden>
7c47d0d...
by
Sean Christopherson <email address hidden>
x86/msr: Add testcases for x2APIC MSRs
Verify that reads and writes to x2APIC MSRs #GP when x2APIC is disabled,
and that reads and writes honor KVM's emulation (which follows Intel
behavior) when x2APIC is enabled. E.g. verify that writes to read-only
registers #GP, reads to write-onliy registers #GP, etc...
Write '0' to write-only registers to play nice with AMD's more restrictive
behavior (Intel doesn't care what value is written).
Note, the x2APIC enabled testcases will likely fail if run on AMD bare
metal as the KVM doesn't emulate registers above self-IPI, i.e. MSRs that
are expected to #GP are presumably handled by AMD hardware.
Signed-off-by: Sean Christopherson <email address hidden>
Signed-off-by: Paolo Bonzini <email address hidden>
Message-Id: <email address hidden>
Signed-off-by: Paolo Bonzini <email address hidden>
f399af2...
by
Sean Christopherson <email address hidden>
x86/apic: Refactor x2APIC reg helper to provide exact semantics
Refactor x2apic_reg_reserved() into get_x2apic_reg_semantics() and have
it provide the semantics for all registers. The full semantics will be
used by the MSR test to verify KVM correctly emulates all x2APIC MSRs.
No functional change intended.
Signed-off-by: Sean Christopherson <email address hidden>
Signed-off-by: Paolo Bonzini <email address hidden>
Message-Id: <email address hidden>
Signed-off-by: Paolo Bonzini <email address hidden>
6509619...
by
Sean Christopherson <email address hidden>
x86/msr: Skip built-in testcases if user provides custom MSR+value to test
Skip the built-in MSR testcases if the user provides a custom MSR+value
to test. If the user is asking to test a specific MSR+value, they likely
don't want to wait for the test to burn though a pile of MCE MSRs.
Fixes: 039d9207 ("x86: msr: Add tests for MCE bank MSRs")
Signed-off-by: Sean Christopherson <email address hidden>
Signed-off-by: Paolo Bonzini <email address hidden>
Message-Id: <email address hidden>
Signed-off-by: Paolo Bonzini <email address hidden>
