~canonical-kernel-team/+git/kvm-unit-tests:tip-testing

Last commit made on 2024-12-27
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Branch merges

Branch information

Name:
tip-testing
Repository:
lp:~canonical-kernel-team/+git/kvm-unit-tests

Recent commits

7c70297... by Po-Hsu Lin

UBUNTU: SAUCE: split failed tests out

BugLink: https://bugs.launchpad.net/bugs/1938875

vmx test contain a bunch of different tests.
Split failed test cases in vmx out as standalone tests to improve our
test granularity. Make it easier to do result hinting and allow this
test to finish properly without being terminated prematurely.

This SAUCE patch will split the following tests out of vmx:
  * rdtsc_vmexit_diff_test
  * test_vmread_flags_touch
  * test_vmwrite_flags_touch
  * test_vmwrite_vmread
  * test_vmxon
  * vmx_apic_passthrough_test
  * vmx_controls_test
  * vmx_cr_load_test
  * vmx_cr4_osxsave_test
  * vmx_db_test
  * vmx_guest_state_area_test
  * vmx_hlt_with_rvi_test
  * vmx_host_state_area_test
  * vmx_intr_window_test
  * vmx_mtf_test
  * vmx_mtf_pdpte_test
  * vmx_nmi_window_test
  * vmx_pending_event_test
  * vmx_preemption_timer_tf_test
  * vmx_preemption_timer_zero_test
  * vmx_store_tsc_test

Signed-off-by: Po-Hsu Lin <email address hidden>

0ed2cdf... by Suzuki K Poulose <email address hidden>

arm64: Fix sve_vl() for build errors

commit 5b9895f8a5d9 ("arm: Fix clang error in sve_vl()") breaks the build
with the following compiler version, as the "rdvl" expects a 64bit register.

/tmp/ccGJYtuC.s: Assembler messages:
/tmp/ccGJYtuC.s:2165: Error: operand mismatch -- `rdvl w3,#8'
/tmp/ccGJYtuC.s:2165: Info: did you mean this?
/tmp/ccGJYtuC.s:2165: Info: rdvl x3, #8
make: *** [<builtin>: arm/selftest.o] Error 1
make: *** Waiting for unfinished jobs....

$ aarch64-none-elf-gcc --version
aarch64-none-elf-gcc (GNU Toolchain for the A-profile Architecture 10.2-2020.11 (arm-10.16)) 10.2.1 20201103

Fix this by switching to use "unsigned long" variable and restoring the 64bit
register for the instruction

Fixes: 5b9895f8a5d9 ("arm: Fix clang error in sve_vl()")
Cc: Raghavendra Rao Ananta <email address hidden>
Cc: Andrew Jones <email address hidden>
Signed-off-by: Suzuki K Poulose <email address hidden>
Signed-off-by: Andrew Jones <email address hidden>

1c49a81... by Andrew Jones <email address hidden>

Merge branch 'riscv/sbi' into 'master'

riscv: Added SBI tests for IPI, SUSP, and HSM

See merge request kvm-unit-tests/kvm-unit-tests!70

afd2cae... by James Raphael Tiovalen

riscv: sbi: Add tests for HSM extension

Add some tests for all of the HSM extension functions. These tests
ensure that the HSM extension functions follow the behavior as described
in the SBI specification.

Signed-off-by: James Raphael Tiovalen <email address hidden>
[Made the changes requested in the last review.]
Signed-off-by: Andrew Jones <email address hidden>

2ffe016... by Andrew Jones <email address hidden>

riscv: sbi: Add SUSP tests

Introduce tests for SBI system suspend. The basic test makes
sure it works and other tests make sure it fails as expected
with invalid entry criteria.

To test on QEMU or hardware the firmware needs to support system
suspend. For QEMU, OpenSBI can be told to enable its system
suspend test mode by creating a new DTB which has

    opensbi-config {
        compatible = "opensbi,config";
        system-suspend-test;
    };

added to the 'chosen' node. Then, run with '-dtb susp.dtb'.

Signed-off-by: Andrew Jones <email address hidden>

173a335... by Andrew Jones <email address hidden>

riscv: sbi: Clean up env checking

Add a couple helpers to cleanup checking of test configuration
environment variables.

Signed-off-by: Andrew Jones <email address hidden>

53cded0... by Andrew Jones <email address hidden>

riscv: Implement setjmp/longjmp

Being able to do setjmp and longjmp can be quite useful for tests.
Implement the functions for riscv.

Signed-off-by: Andrew Jones <email address hidden>

82d72ec... by Andrew Jones <email address hidden>

riscv: sbi: Add two in hart_mask IPI test

We should ensure that when hart_mask has more than one hartid
that both harts get IPIs with a single call of the IPI function.

Signed-off-by: Andrew Jones <email address hidden>

498a191... by Cade Richard <email address hidden>

riscv: sbi: Add IPI extension tests

Ensure IPIs directed at single harts are received and also that all
harts receive IPIs on broadcast. Also check for invalid param errors
when the params result in hartids greater than the max.

Signed-off-by: Cade Richard <email address hidden>
Co-developed-by: Andrew Jones <email address hidden>
Signed-off-by: Andrew Jones <email address hidden>

56ca809... by Andrew Jones <email address hidden>

riscv: Add sbi_send_ipi_broadcast

Coming SBI IPI tests will use this, but as it could be useful for
other tests too, add it to the library.

Signed-off-by: Andrew Jones <email address hidden>