HWE Next

~canonical-hwe-team/hwe-next/+git/sof:topic/upstarem/drop/006/pr/ci_test

  1. Git
  2. lp:~canonical-hwe-team/hwe-next/+git/sof
  3. topic/upstarem/drop/006/pr/ci_test
Last commit made on 2023-09-14
Get this branch:
git clone -b topic/upstarem/drop/006/pr/ci_test https://git.launchpad.net/~canonical-hwe-team/hwe-next/+git/sof

Branch merges

Branch information

Name:
topic/upstarem/drop/006/pr/ci_test
Repository:
lp:~canonical-hwe-team/hwe-next/+git/sof

Recent commits

2a816f6... by Tomasz Leman <email address hidden>

nothing: empty commit

Empty commit done for test.

Signed-off-by: Tomasz Leman <email address hidden>

a652a5f... by Tomasz Leman <email address hidden>

west: update zephyr version

Fix for LNL.

Signed-off-by: Tomasz Leman <email address hidden>

562678e... by Tomasz Leman <email address hidden>

lnl: overlay: update clock frequency

Changing max clock frequency for FPGA configuration.

+ Correct value for MTL.

Signed-off-by: Tomasz Leman <email address hidden>

bff1fc6... by Tomasz Leman <email address hidden>

lnl: clock: update clock definitions

ACE_1.5 and ACE_2.0 use only two clocks for DSP cores. First is WOVRCO and
second is ACE IPLL.

IPLL allows to configure it to work like LP RING Oscillator Clock or HP
RING Oscillator Clock. Currently, the driver does not allow this, so I
remove the frequency that cannot be achieved anyway.

Clocks frequencies:
WOW: 38.4 MHz
IPLL: 393.216 MHz

Signed-off-by: Tomasz Leman <email address hidden>

bba6300... by Tomasz Leman <email address hidden>

west: update zephyr version

Add fix for mtl clock switching.

Signed-off-by: Tomasz Leman <email address hidden>

eca72fd... by Tomasz Leman <email address hidden>

mtl: overlay: update clock frequency

Changing max clock frequency for FPGA configuration.

Signed-off-by: Tomasz Leman <email address hidden>

c71a9da... by Tomasz Leman <email address hidden>

ace: mtl: clock: update clock definitions

Meteorlake use only two clocks for DSP cores. First is WOVRCO and second
is ACE IPLL.

Clocks frequencies:
WOW: 38.4 MHz
IPLL: 393.2 MHz

Signed-off-by: Tomasz Leman <email address hidden>

202439e... by Adrian Warecki <email address hidden>

rimage: Update rimage revision

Changed rimage revision to apply new fix in verify_image.

Signed-off-by: Adrian Warecki <email address hidden>

fa1572c... by Tomasz Leman <email address hidden>

zephyr: cpu: fix condition to init cpu

This check should depend on platform generation, not on a not related
feature. Original assumption, that on ACE IMR context save is always
enabled was wrong

Signed-off-by: Tomasz Leman <email address hidden>

b45872e... by Adrian Warecki <email address hidden>

module_adapter: ModuleInitialSettingsConcrete: Fix code issues

Signed-off-by: Adrian Warecki <email address hidden>