f2941a7...
by
Ross Chisholm <email address hidden>
on 2021-04-20
topology: fixing comments in jsl-rt1015 topology
Corrected comments relating to s32le (was s24le)
Signed-off-by: Ross Chisholm <email address hidden>
0823ff3...
by
Ross Chisholm <email address hidden>
on 2021-04-20
topology: adding optional support for IIR component on jsl-rt015 topology
Allows the IIR component to be added to the jsl-rt015 topology allowing
tuning
Signed-off-by: Ross Chisholm <email address hidden>
113f570...
by
Yong Zhi <email address hidden>
on 2020-09-22
topology: fix playback & capture pipelines to be timer driven
The patch fixes two SSP pipelines to be scheduled in timer domain.
Signed-off-by: Yong Zhi <email address hidden>
1a1d357...
by
Uday M Bhat <email address hidden>
on 2020-07-03
topology: jsl-rt1015: PLL input at 50fs is no longer supported
The new recommended settings at 48Khz rate are:
PLL input SSP bclk
------- ------- ------- ---
64fs 3.073Mhz
100fs 4.8Mhz
Modifying topology to 64fs
Signed-off-by: Slawomir Blauciak <email address hidden>
229d9ae...
by
Janusz Jankowski <email address hidden>
on 2020-08-04
ll: set initial value for num_clients
Value for 'num_clients' has to be set, otherwise it may
have undefined value in later ifs.
Signed-off-by: Janusz Jankowski <email address hidden>
ed35a46...
by
Bartosz Kokoszko <email address hidden>
on 2020-05-27
mux: simplifies mux processing functions
This commit simplifies mux processing functions and
does not allow mux to mix channels.
Signed-off-by: Bartosz Kokoszko <email address hidden>
21c8900...
by
Janusz Jankowski <email address hidden>
on 2020-07-23
chrome: jsl: disable system agent
To match TGL release config.
Signed-off-by: Janusz Jankowski <email address hidden>
dd19083...
by
Janusz Jankowski <email address hidden>
on 2020-07-23
chrome: jsl: disable LPS
To match TGL release config.
Signed-off-by: Janusz Jankowski <email address hidden>
979ab3f...
by
Marcin Rajwa <email address hidden>
on 2020-07-07
topology: fix playback & capture pipelines to be timer driven
This patch fixes two SSP pipelines to be scheduled in timer
domain.
Signed-off-by: Marcin Rajwa <email address hidden>
8253356...
by
Marcin Rajwa <email address hidden>
on 2020-07-14
memory: add TGL HPSRAM LDOCTL missing seetings
TGL introduces new LDO control register bits - HS2 which
is reponsible of LDO2 control. This patch adds this missing
LDO2 settings for TGL HPSRAM memory banks.
Signed-off-by: Marcin Rajwa <email address hidden>