cavs: enable power gating for lp/hpsram on d3 entry
Power gating for HPSRAM & LPSRAM on D3 entry enabled for all cAVS
platforms (cAVS 1.5/1.8/2.x) except SueCreek. Implementation shared
between cAVS 1.8/2.0/2.5 is located in cavs lib, cAVS 1.5 specific
implementation remains in ApolloLake platform directory.
cavs: deduplicate power down sequence for cavs platforms
cAVS power down sequence refactored by moving CannonLake (cAVS 1.8)
implementation to cavs lib as a base for cAVS 1.8/2.0/2.5 common
code. ApolloLake (cAVS 1.5) specific implementation remains as a
platform specific code.
cnl: Access to HPSRAM power gating status register - macro updated
Macro modified for SRAM segments > 0 fixed by register offset
update to a proper value.
kpb: fix premature state change in buffering function
This patch fixes state change in buffering function before
the check of state from previous stage. This issue resulted
in missing samples from stream during draining.
Signed-off-by: Marcin Rajwa <email address hidden>