18dc72f...
by
"Kwasowiec, Fabiola" <email address hidden>
comp: fix bind order
Current ipc_comp_connect() connects the source first, then calls comp_bind
and only then connects the sink. This leads to errors with modules that
assume sink to be connected at bind. This is a valid assumption, so fix
the order in ipc_comp_connect().
mixout-gain-dai-copier-playback.2 pipeline id has been changed to 1.
Need to change mixout.2.1 to mixout.1.1 as well.
Fixes: f0a010052bd0 ("topology2: cavs-sdw: group route and pipeline index")
Signed-off-by: Bard Liao <email address hidden>
0ecfc78...
by
Serhiy Katsyuba <email address hidden>
ipc4: fix crash when using ALH DAI
dma_buffer is not yet created when ipc_dai_data_config() is called.
Accessing dma_buffer->stream leads to crash.
Anyway, there is no need to set
dd->dma_buffer->stream.frame_fmt = SOF_IPC_FRAME_S32_LE
as this is done just after ipc_dai_data_config() in dai_params()
by calling buffer_set_params().
Somewhat similar fix for IPC3 was done some time ago: 0ba90d8e2a.
topology1: mt8186: support 1ms pipeline capture period
Default support 1ms period capture pipeline to update host
position more precisely.
Signed-off-by: Chunxu Li <email address hidden>
0af54f9...
by
Guennadi Liakhovetski <email address hidden>
buffer: handle prefetch
Data cache on Xtensa can be prefetched speculatively. In a sequence:
modify cached
modify uncached
modify cached
it isn't enough to writeback-invalidate caches after the first line.
Cache can be prefetched immediately before the second like,
preserving an outdated version of the data and then using it in line
3. The correct sequence is:
007247c...
by
Guennadi Liakhovetski <email address hidden>
coherent: align object allocation size to a cache line
Objects, used with the coherent API must be allocated to align to a
cache line boundary at the end. Since heap allocations always begin
on a cache line boundary, we just need to align the size to an
integer number of cache line sizes. Otherwise the header from the
next heap allocation can reside in the same cache line and therefore
be overwritten with stale data.
