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6b9f935... by =?utf-8?q?Per_=C3=85hgren?= <email address hidden> on 2022-12-06

Merge remote-tracking branch 'origin/main' into GeneralizeGoogleRtcAudioProcessingComponent

68cfa2d... by Iuliana Prodan <email address hidden> on 2022-11-22

imx: clear general purpose pending interrupt

Clear general purpose pending interrupt
before enabling interrupts between host and DSP.
The GIPn bit, from MU Status Register is cleared
by writing it as “1” in order to de-assert the
interrupt request source at the interrupt controller.

This fixes a fw loading failure after a soft reboot
caused by GIP bit that was 1.
The problem was the MU which triggered endless interrupts
causing timeout on Kernel side, which was waiting for
FW_READY message.

Signed-off-by: Iuliana Prodan <email address hidden>

bde8f04... by Iuliana Prodan <email address hidden> on 2022-12-05

scripts: qemu-check.sh: update READY_IPC for imx8

Update READY_IPC value based on changes regarding MU reset.
READY_IPC value comes from:
- clear GP pending interrupt #0 and #1 from MU's xSR register;
- enable GP #0 and #1 for Host -> DSP and DSP -> Host
message notification from MU's xCR register;
- now interrupt host to tell it we are done booting
by setting GIRn bit in MU's xCR register.

So, "00 00 00 c0 00 00 04 c0" is the MU's xSR and xCR registers:
xSR: c0000000 and xCR: c0040000

Signed-off-by: Iuliana Prodan <email address hidden>

8554b47... by Rander Wang <email address hidden> on 2022-10-31

topology2: hda: share deep buffer conf setting

Deep buffer is mixed with HDA analog.

Signed-off-by: Rander Wang <email address hidden>

c1e0c8b... by Rander Wang <email address hidden> on 2022-09-22

topology2: sdw: share the deep buffer conf setting

Deep buffer is mixed with Jack out.

Signed-off-by: Rander Wang <email address hidden>

97d7382... by Rander Wang <email address hidden> on 2022-09-22

topology2: nocodec: add deep buffer support

Deep buffer is mixed with ssp0 stream.

Signed-off-by: Rander Wang <email address hidden>

6d0e62c... by Rander Wang <email address hidden> on 2022-09-22

topology2: add common deep buffer support

It will be shared by I2S, HDA and SDW platforms

Signed-off-by: Rander Wang <email address hidden>

9ed983c... by Gerard Marull-Paretas <email address hidden> on 2022-11-23

sof: common: namespace common DIV_ROUND_UP macro

DIV_ROUND_UP is a common macro exposed in public headers without
namespacing. Change the name to SOF_DIV_ROUND_UP to avoid collisions
with other systems/libraries.

Signed-off-by: Gerard Marull-Paretas <email address hidden>

8de3e89... by =?utf-8?q?Per_=C3=85hgren?= <email address hidden> on 2022-12-06

Adjustments and formatting

4a9a99a... by Iuliana Prodan <email address hidden> on 2022-11-22

imx: clear general purpose pending interrupt

Clear general purpose pending interrupt
before enabling interrupts between host and DSP.
The GIPn bit, from MU Status Register is cleared
by writing it as “1” in order to de-assert the
interrupt request source at the interrupt controller.

This fixes a fw loading failure after a soft reboot
caused by GIP bit that was 1.
The problem was the MU which triggered endless interrupts
causing timeout on Kernel side, which was waiting for
FW_READY message.

Signed-off-by: Iuliana Prodan <email address hidden>