lp:simulide

Created by arcachofo on 2021-01-01 and last modified on 2021-03-02
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Branch information

Owner:
arcachofo
Project:
SimulIDE
Status:
Development

Recent revisions

176. By arcachofo <email address hidden> on 2021-03-02

Added Logic Analizer.

175. By arcachofo <email address hidden> on 2021-03-02

Update translation files.

174. By arcachofo <email address hidden> on 2021-03-02

Added Czech translation and help files.

173. By arcachofo <email address hidden> on 2021-03-02

74HC173 simplified model.

172. By arcachofo <email address hidden> on 2021-03-02

FlipFlops proper initialization.

171. By arcachofo <email address hidden> on 2021-02-26

Latch D: Size error when no OE and no Tristate.

170. By arcachofo <email address hidden> on 2021-02-25

Chip: show Id property overriden at initChip.

169. By arcachofo <email address hidden> on 2021-02-25

Memtable: error representing negative values.

168. By arcachofo <email address hidden> on 2021-02-25

Simulator: error in event counter.

167. By arcachofo <email address hidden> on 2021-02-23

New Subcircuits: 7489, 74200, 74219, 74301.

Branch metadata

Branch format:
Branch format 7
Repository format:
Bazaar repository format 2a (needs bzr 1.16 or later)
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