lp:~anthonywong/hwe-next/+git/sof-bin

Owned by Anthony Wong
Get this repository:
git clone https://git.launchpad.net/~anthonywong/hwe-next/+git/sof-bin

Import details

Import Status: Reviewed

This repository is an import of the Git repository at https://github.com/thesofproject/sof-bin.git.

The next import is scheduled to run in 59 minutes.

Last successful import was 5 hours ago.

Import started 5 hours ago on alnitak and finished 5 hours ago taking 20 seconds — see the log
Import started 11 hours ago on alnitak and finished 11 hours ago taking 15 seconds — see the log
Import started 17 hours ago on alnitak and finished 17 hours ago taking 15 seconds — see the log
Import started 23 hours ago on alnitak and finished 23 hours ago taking 20 seconds — see the log
Import started on 2020-12-04 on alnitak and finished on 2020-12-04 taking 15 seconds — see the log
Import started on 2020-12-04 on alnitak and finished on 2020-12-04 taking 20 seconds — see the log
Import started on 2020-12-03 on alnitak and finished on 2020-12-03 taking 15 seconds — see the log
Import started on 2020-12-03 on alnitak and finished on 2020-12-03 taking 15 seconds — see the log
Import started on 2020-12-03 on alnitak and finished on 2020-12-03 taking 20 seconds — see the log
Import started on 2020-12-03 on alnitak and finished on 2020-12-03 taking 20 seconds — see the log

Branches

Name Last Modified Last Commit
master 2020-11-23 11:55:36 UTC 2020-11-23
publish: reset ldc file mode also

Author: Pan Xiuli
Author Date: 2020-11-20 14:21:23 UTC

publish: reset ldc file mode also

Add ldc file into the file mode reset.

Signed-off-by: Pan Xiuli <xiuli.pan@linux.intel.com>

stable-v1.6 2020-11-20 14:27:07 UTC 2020-11-20
Add built tgl rt715-rt711-rt1308 tplg file

Author: Kai-Chuan Hsieh
Author Date: 2020-10-05 07:26:11 UTC

Add built tgl rt715-rt711-rt1308 tplg file

The topology has been added to sof project.
create the sof-tgl-rt715-rt711-rt1308-mono.tplg and has validated on
Dell latest Latitude machine that works.

Signed-off-by: Kai-Chuan Hsieh <kaichuan.hsieh@canonical.com>

stable-v1.5.1 2020-09-21 07:03:37 UTC 2020-09-21
stable: v1.5.1: Add tools binary for the release

Author: Pan Xiuli
Author Date: 2020-09-21 06:39:44 UTC

stable: v1.5.1: Add tools binary for the release

Add the tools binary for the relase.

Signed-off-by: Pan Xiuli <xiuli.pan@linux.intel.com>

stable-v1.4.3 2020-05-15 09:47:12 UTC 2020-05-15
stable: v1.4.3: Add stable v1.4.3 release

Author: Pan Xiuli
Author Date: 2020-05-15 09:47:12 UTC

stable: v1.4.3: Add stable v1.4.3 release

Fix since v1.4.2

7605252851ca - Janusz Jankowski : platform: intel: add clock switch for waiti
1b71a50283d6 - Janusz Jankowski : arch: xtensa: add waiti wakeup hook
0ca4545f9e73 - Janusz Jankowski : platform: intel: LP HP freq indexes
5a7ef9cbb43f - Tomasz Lauda : cavs: interrupt: move irq names to cavs header
8311e0c6af3d - Janusz Jankowski : cavs: lib: check status mask in cpu clock set
658a079fc597 - Janusz Jankowski : tigerlake: shim: clock status registers
7c6780064efa - Janusz Jankowski : tigerlake: shim: clock control registers
a8c280def34d - Janusz Jankowski : icelake: shim: clock status registers
e7ea4aefa0ed - Janusz Jankowski : icelake: shim: clock control registers
e802a7ca95db - Janusz Jankowski : suecreek: shim: clock status registers
ec4cb78134e3 - Janusz Jankowski : suecreek: shim: clock control registers
47f3601860a7 - Janusz Jankowski : cannonlake: shim: clock control registers
61577dc16b6e - Janusz Jankowski : cannonlake: shim: clock status registers

Signed-off-by: Pan Xiuli <xiuli.pan@linux.intel.com>

stable-v1.5 2020-05-13 06:41:46 UTC 2020-05-13
stable: v1.5: Add stable v1.5 release.

Author: Pan Xiuli
Author Date: 2020-05-13 06:41:46 UTC

stable: v1.5: Add stable v1.5 release.

New stable release v1.5

Signed-off-by: Pan Xiuli <xiuli.pan@linux.intel.com>

stable-v1.4.2 2020-03-17 13:03:21 UTC 2020-03-17
Fix typo

Author: Dan Dascalescu
Author Date: 2020-03-17 04:24:21 UTC

Fix typo

16 of 6 results
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