Merge lp:~ams-codesourcery/gcc-linaro/lp836401-4.6 into lp:gcc-linaro/4.6

[Andrew Stubbs]

Fix for Bug LP836401.

[Michael Hope (michaelh1)]

cbuild has taken a snapshot of this branch at r106798 and queued it for build.

The snapshot is available at:
 http://ex.seabright.co.nz/snapshots/gcc-linaro-4.6+bzr106798~ams-codesourcery~lp836401-4.6.tar.xdelta3.xz

and will be built on the following builders:
 a9-builder armv5-builder baremetal i686 x86_64

You can track the build queue at:
 http://ex.seabright.co.nz/helpers/scheduler

cbuild-snapshot: gcc-linaro-4.6+bzr106798~ams-codesourcery~lp836401-4.6
cbuild-ancestor: lp:gcc-linaro/4.6+bzr106797
cbuild-state: check

[Michael Hope (michaelh1)]

cbuild successfully built this on i686-natty-cbuild172-oort2-i686r1.

The build results are available at:
 http://ex.seabright.co.nz/build/gcc-linaro-4.6+bzr106798~ams-codesourcery~lp836401-4.6/logs/i686-natty-cbuild172-oort2-i686r1

+PASS: gcc.dg/pr50193-1.c (test for warnings, line 9)
+PASS: gcc.dg/pr50193-1.c (test for excess errors)

The full testsuite results are at:
 http://ex.seabright.co.nz/build/gcc-linaro-4.6+bzr106798~ams-codesourcery~lp836401-4.6/logs/i686-natty-cbuild172-oort2-i686r1/gcc-testsuite.txt

cbuild-checked: i686-natty-cbuild172-oort2-i686r1

[Michael Hope (michaelh1)]

cbuild successfully built this on x86_64-natty-cbuild172-oort1-x86_64r1.

The build results are available at:
 http://ex.seabright.co.nz/build/gcc-linaro-4.6+bzr106798~ams-codesourcery~lp836401-4.6/logs/x86_64-natty-cbuild172-oort1-x86_64r1

+PASS: gcc.dg/pr50193-1.c (test for warnings, line 9)
+PASS: gcc.dg/pr50193-1.c (test for excess errors)

The full testsuite results are at:
 http://ex.seabright.co.nz/build/gcc-linaro-4.6+bzr106798~ams-codesourcery~lp836401-4.6/logs/x86_64-natty-cbuild172-oort1-x86_64r1/gcc-testsuite.txt

cbuild-checked: x86_64-natty-cbuild172-oort1-x86_64r1

[Michael Hope (michaelh1)]

cbuild successfully built this on armv7l-natty-cbuild172-ursa1-cortexa9r1.

The build results are available at:
 http://ex.seabright.co.nz/build/gcc-linaro-4.6+bzr106798~ams-codesourcery~lp836401-4.6/logs/armv7l-natty-cbuild172-ursa1-cortexa9r1

+PASS: gcc.dg/pr50193-1.c (test for warnings, line 9)
+PASS: gcc.dg/pr50193-1.c (test for excess errors)

The full testsuite results are at:
 http://ex.seabright.co.nz/build/gcc-linaro-4.6+bzr106798~ams-codesourcery~lp836401-4.6/logs/armv7l-natty-cbuild172-ursa1-cortexa9r1/gcc-testsuite.txt

cbuild-checked: armv7l-natty-cbuild172-ursa1-cortexa9r1

[Ulrich Weigand (uweigand)]

This looks good as far as it goes, but there seem to be ongoing discussions on the mailing list regarding the mainline submission of this patch.

Since those discussion are about *further* restricting that test, I'd be fine with the patch submitted here to go in now as is, and then be updated with whatever gets committed upstream in the end.

In the alternative, you might want to wait until the mainline patch is accepted and then check it in to Linaro GCC as well -- feel free to choose either approach.

review: Approve

[Andrew Stubbs (ams-codesourcery)]

I'm delaying this due to Richard Sandiford's opinion that the the constraints need tightening also, and that changing the predicate alone only makes it worse (apparently reload ignores the predicates, and this could lead to recog ICES further down the line).

review: Needs Fixing

[Michael Hope (michaelh1)]

cbuild successfully built this on armv7l-natty-cbuild172-ursa2-armv5r2.

The build results are available at:
 http://ex.seabright.co.nz/build/gcc-linaro-4.6+bzr106798~ams-codesourcery~lp836401-4.6/logs/armv7l-natty-cbuild172-ursa2-armv5r2

+PASS: gcc.dg/pr50193-1.c (test for warnings, line 9)
+PASS: gcc.dg/pr50193-1.c (test for excess errors)

The full testsuite results are at:
 http://ex.seabright.co.nz/build/gcc-linaro-4.6+bzr106798~ams-codesourcery~lp836401-4.6/logs/armv7l-natty-cbuild172-ursa2-armv5r2/gcc-testsuite.txt

cbuild-checked: armv7l-natty-cbuild172-ursa2-armv5r2

[Ramana Radhakrishnan (ramana)]

I think this should wait till other comments upstream have been handled.

ramana

=== modified file 'ChangeLog.linaro'
--- ChangeLog.linaro	2011-08-26 14:32:47 +0000
+++ ChangeLog.linaro	2011-09-01 13:18:48 +0000
@@ -1,3 +1,12 @@
[phone]  Andrew Stubbs  <[e-mail]>
+
+	gcc/
+	* config/arm/predicates.md (shift_amount_operand): Ensure shift
+	amount is positive.
+
+	gcc/testsuite/
+	* gcc.dg/pr50193-1.c: New file.
+
 2011-08-26  Richard Sandiford  <[e-mail]>
 
 	gcc/

=== modified file 'gcc/config/arm/predicates.md'
--- gcc/config/arm/predicates.md	2011-08-13 08:40:36 +0000
+++ gcc/config/arm/predicates.md	2011-09-01 13:18:48 +0000
@@ -132,7 +132,8 @@
 (define_predicate "shift_amount_operand"
   (ior (and (match_test "TARGET_ARM")
 	    (match_operand 0 "s_register_operand"))
-       (match_operand 0 "const_int_operand")))
+       (and (match_operand 0 "const_int_operand")
+	    (match_test "INTVAL (op) > 0"))))
 
 (define_predicate "arm_add_operand"
   (ior (match_operand 0 "arm_rhs_operand")

=== added file 'gcc/testsuite/gcc.dg/pr50193-1.c'
--- gcc/testsuite/gcc.dg/pr50193-1.c	1970-01-01 00:00:00 +0000
+++ gcc/testsuite/gcc.dg/pr50193-1.c	2011-09-01 13:18:48 +0000
@@ -0,0 +1,10 @@
+/* PR 50193: ARM: ICE on a | (b << negative-constant) */
+/* Ensure that the compiler doesn't ICE.  */
+
+/* { dg-options "-O2" } */
+
+int
+foo(int a, int b)
+{
+  return a | (b << -3); /* { dg-warning "left shift count is negative" } */
+}