glibc:alistair/rv32.next

Last commit made on 2020-04-26
Get this branch:
git clone -b alistair/rv32.next https://git.launchpad.net/glibc

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Branch information

Name:
alistair/rv32.next
Repository:
lp:glibc

Recent commits

5b738d3... by Alistair Francis <email address hidden> on 2020-04-08

Revert "Add IPPROTO_ETHERNET and IPPROTO_MPTCP from Linux 5.6 to netinet/in.h."

This reverts commit f9ac84f92f151e07586c55e14ed628d493a5929d.

858342b... by Alistair Francis <email address hidden> on 2019-12-30

COVER: glibc port for 32-bit RISC-V (RV32)

This patch set contains the glibc port for 32-bit RISC-V.

This is based on the original work from Zong Li [1] and has been
updated to use a 64-bit time_t.

This requires a 5.4+ kernel and all of the testing has been done using
the 5.4 stable kernel.

Nothing fails when running ./scripts/build-many-glibcs.py (for all
targets) on my x86-64 machine.

This is the current list of tests that fail when running inside QEMU RV32
system emulation on the 5.4 kernel:

FAIL: elf/tst-ldconfig-ld_so_conf-update
FAIL: io/tst-lockf
FAIL: misc/test-errno-linux
FAIL: nss/tst-nss-files-hosts-long
FAIL: resolv/tst-resolv-res_init-thread
FAIL: stdio-common/bug22
FAIL: stdlib/tst-strfrom
FAIL: stdlib/tst-strfrom-locale
FAIL: sysvipc/test-sysvmsg

---Links---
1: https://sourceware.org/ml/libc-alpha/2018-07/msg00892.html

The latest version of my work can be found here: https://github.com/alistair23/glibc/tree/alistair/rv32.next

This specific version can be found here: https://github.com/alistair23/glibc/tree/alistair/rv32.1

---Changelog---
v1:
 - Update based from feedback on RFCv6
 - Improve test passing
     - There are only 9 tests failing now
 - Rebase on Lukasz's work
 - Send only the RV32 specific patches (other patches are already merged
   or on the list)
RFC v6:
 - Rebase on top of accetpted patches
 - Fix issues so that the tests actually run
RFC v5:
 - Hopefully finally get the correct layout for the *64 syscalls
 - Sort out the Changelog
RFC v4:
 - Continue to fix things that weren't working
 - Update the coding style to match glibc
 - Update the __ASSUME_TIME64_SYSCALLS work to better match Lukasz's
 work
RFC v3:
 - Remove all "Hack" patches
 - Incorporate upstream comments
 - Ensure we don't break RV64
 - Lot's more testing and fixes
RFC v2:
 - Add Lukasz's patches
 - Update the non HACK syscalls after feedback
 - define __ASSUME_TIME64_SYSCALLS and __ASSUME_RLIM64_SYSCALLS
 - Remove lockf64.c
 - Other smaller changes from RFC v1

09ce020... by Zong Li <email address hidden> on 2018-11-30

Add RISC-V 32-bit target to build-many-glibcs.py

Support building three variant of 32 bit RISC-V glibc as follows:
- riscv32-linux-gnu-rv32imac-ilp32
- riscv32-linux-gnu-rv32imafdc-ilp32
- riscv32-linux-gnu-rv32imafdc-ilp32d

f1a49b3... by Zong Li <email address hidden> on 2018-11-30

Documentation for the RISC-V 32-bit port

There is already RISC-V 64-bit port information in the documentation.
Let's add some documentation entries for the RISC-V 32-bit as well.

daecde0... by Zong Li <email address hidden> on 2019-09-10

RISC-V: Add rv32 path to RTLDLIST in ldd

376aa9d... by Alistair Francis <email address hidden> on 2019-12-21

riscv32: Specify the arch_minimum_kernel as 5.4

5bafcca... by Zong Li <email address hidden> on 2018-11-30

RISC-V: Build Infastructure for 32-bit

This patch lays out the top-level orginazition of the RISC-V 32-bit port. It
contains all the Implies files as well as various other fragments of
build infastructure for the RISC-V 32-bit port.

bed534f... by Zong Li <email address hidden> on 2018-11-30

RISC-V: Fix llrint and llround missing exceptions on RV32

Similar to the fix for MIPS, ARM and S/390, RV32 is missing
correct exception on overflow from llrint and llround functions because
cast from floating-point types to long long do not result in correct
exceptions on overflow.

0258a4f... by Alistair Francis <email address hidden> on 2020-01-04

RISC-V: Add the RV32 libm-test-ulps

Add a libm-test-ulps for RV32, generated by running `make regen-ulps`.
This is different to the RV64 one.

6ffd7a1... by Alistair Francis <email address hidden> on 2019-11-15

RISC-V: Add ABI lists

Use the check-api and update-abi to generate the abilist for rv32.