slp_s0 counter value displayed via debugfs interface is calculated by
multiplying the granularity for crystal oscillator tick as 100us with
the value read from using slp_s0 offset. But the granularity of the tick
varies from platform to platform and it needs to be fixed.
Hence, specify granularity of the tick for each platform, so that the
value of the slp_s0 counter is accurate.
Signed-off-by: Gayatri Kammela <email address hidden>
Signed-off-by: David E. Box <email address hidden>
Reviewed-by: Andy Shevchenko <email address hidden>
Link: https://<email address hidden>
Signed-off-by: Hans de Goede <email address hidden>
(cherry picked from commit 025f26de7fa0fc40c8baf6c19fb273500f3321f0)
Signed-off-by: AceLan Kao <email address hidden>
a2a34e6...
by
Gayatri Kammela <email address hidden>
platform/x86: intel_pmc_core: Fix TigerLake power gating status map
TigerLake's LPM power gating status register has errors in the bit-to-name
mapping as well as with the marked reserved bits according to the actual
implementation. Hence, update the right bit-to-name mapping and the
reserved bits in accordance with actual implementation.
Cc: Srinivas Pandruvada <email address hidden>
Cc: Andy Shevchenko <email address hidden>
Cc: David E. Box <email address hidden>
Signed-off-by: Gayatri Kammela <email address hidden>
Signed-off-by: David E. Box <email address hidden>
Reviewed-by: Andy Shevchenko <email address hidden>
Link: https://<email address hidden>
Signed-off-by: Hans de Goede <email address hidden>
(cherry picked from commit 652036bd5be0ac94fd1db851d72ece8ee133c74d)
Signed-off-by: AceLan Kao <email address hidden>
TigerLake Lower Power Mode (LPM) registers are grouped by functionality
but were given simple enumerated names in the code (lpm0, lpm1, ...).
Instead, give the register blocks names that describe their usage.
Suggested-by: Andy Shevchenko <email address hidden>
Signed-off-by: David E. Box <email address hidden>
Reviewed-by: Andy Shevchenko <email address hidden>
Link: https://<email address hidden>
Signed-off-by: Hans de Goede <email address hidden>
(cherry picked from commit e973f1d372dca5ac1d107ec6134f72e566fdf968)
Signed-off-by: AceLan Kao <email address hidden>
When both CONFIG_DEBUG_FS and CONFIG_PM_SLEEP are disabled, the
functions that got moved out of the #ifdef section now cause
a warning:
drivers/platform/x86/intel_pmc_core.c:654:13: error: 'pmc_core_lpm_display' defined but not used [-Werror=unused-function]
654 | static void pmc_core_lpm_display(struct pmc_dev *pmcdev, struct device *dev,
| ^~~~~~~~~~~~~~~~~~~~
drivers/platform/x86/intel_pmc_core.c:617:13: error: 'pmc_core_slps0_display' defined but not used [-Werror=unused-function]
617 | static void pmc_core_slps0_display(struct pmc_dev *pmcdev, struct device *dev,
| ^~~~~~~~~~~~~~~~~~~~~~
Rather than add even more #ifdefs here, remove them entirely and
let the compiler work it out, it can actually get rid of all the
debugfs calls without problems as long as the struct member is
there.
The two PM functions just need a __maybe_unused annotations to avoid
another warning instead of the #ifdef.
Fixes: aae43c2bcdc1 ("platform/x86: intel_pmc_core: Relocate pmc_core_*_display() to outside of CONFIG_DEBUG_FS")
Signed-off-by: Arnd Bergmann <email address hidden>
Signed-off-by: Andy Shevchenko <email address hidden>
(cherry picked from commit 01f259f3720c3965443109d82a0f12611ea8bb58)
Signed-off-by: AceLan Kao <email address hidden>
55ec506...
by
Archana Patni <email address hidden>
platform/x86: intel_pmc_core: Change Jasper Lake S0ix debug reg map back to ICL
Jasper Lake uses Icelake PCH IPs and the S0ix debug interfaces are same as
Icelake. It uses SLP_S0_DBG register latch/read interface from Icelake
generation. It doesn't use Tiger Lake LPM debug registers. Change the
Jasper Lake S0ix debug interface to use the ICL reg map.
Fixes: 16292bed9c56 ("platform/x86: intel_pmc_core: Add Atom based Jasper Lake (JSL) platform support")
Signed-off-by: Archana Patni <email address hidden>
Acked-by: David E. Box <email address hidden>
Tested-by: Divagar Mohandass <email address hidden>
Signed-off-by: Andy Shevchenko <email address hidden>
(cherry picked from commit e87fa339d413c540c065c280ba9e7cc9a8dbcfd1)
Signed-off-by: AceLan Kao <email address hidden>
1f549d6...
by
Gayatri Kammela <email address hidden>
platform/x86: intel_pmc_core: Make pmc_core_substate_res_show() generic
Currently pmc_core_substate_res_show() uses array of char pointers
i.e., lpm_modes for Tiger Lake directly to iterate through and to get
the number of low power modes which is hardcoded and cannot be re-used
for future platforms that support sub-states. To maintain readability,
make pmc_core_substate_res_show() generic, so that it can re-used for
future platforms.
Cc: Chen Zhou <email address hidden>
Cc: Andy Shevchenko <email address hidden>
Cc: David E. Box <email address hidden>
Signed-off-by: Gayatri Kammela <email address hidden>
Signed-off-by: Andy Shevchenko <email address hidden>
(cherry picked from commit c61b693c9a032991f34cc4034b466d7807fd61ab)
Signed-off-by: AceLan Kao <email address hidden>
0a63a85...
by
Gayatri Kammela <email address hidden>
platform/x86: intel_pmc_core: Make pmc_core_lpm_display() generic for platforms that support sub-states
Currently pmc_core_lpm_display() uses an array of the struct pointers,
i.e. tgl_lpm_maps for Tiger Lake directly to iterate through and to get
the number of (live) status registers which is hard coded and can not
be re-used for the future platforms that support sub-states. To maintain
readability, make pmc_core_lpm_display() generic, so that it can be re-used
for future platforms.
Cc: Chen Zhou <email address hidden>
Cc: Andy Shevchenko <email address hidden>
Cc: David E. Box <email address hidden>
Suggested-by: Andy Shevchenko <email address hidden>
Signed-off-by: Gayatri Kammela <email address hidden>
Signed-off-by: Andy Shevchenko <email address hidden>
(cherry picked from commit 267fc714cab797574a3a9df2074f05c3cdeb2511)
Signed-off-by: AceLan Kao <email address hidden>
e959a7b...
by
Gayatri Kammela <email address hidden>
platform/x86: intel_pmc_core: Add slp_s0_offset attribute back to tgl_reg_map
If platforms such as Tiger Lake has sub-states of S0ix, then attributes
such as slps0_dbg_offset become invalid. But slp_s0_offset is still
valid as it is used to get the pmcdev_base_addr.
Hence, add back slp_s0_offset and remove slps0_dbg_offset attributes.
Cc: Chen Zhou <email address hidden>
Cc: Andy Shevchenko <email address hidden>
Cc: David E. Box <email address hidden>
Signed-off-by: Gayatri Kammela <email address hidden>
Signed-off-by: Andy Shevchenko <email address hidden>
(cherry picked from commit 0e9c026f1b86a855cb9ab7aa270ff8db3c72015d)
Signed-off-by: AceLan Kao <email address hidden>
