yosys binary package in Ubuntu Lunar amd64
This is a framework for Verilog RTL synthesis. It currently has extensive
Verilog-2005 support and provides a basic set of synthesis algorithms for
various application domains.
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Yosys can be adapted to perform any synthesis job by combining the existing
passes (algorithms) using synthesis scripts and adding additional passes as
needed by extending the yosys C++ code base.
Publishing history
Date | Status | Target | Component | Section | Priority | Phased updates | Version | ||
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2022-12-04 17:13:33 UTC | Published | Ubuntu Lunar amd64 | release | universe | electronics | Optional | 0.23-6 | ||
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Deleted | Ubuntu Lunar amd64 | proposed | universe | electronics | Optional | 0.23-6 | |||
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2022-12-04 06:04:36 UTC | Superseded | Ubuntu Lunar amd64 | proposed | universe | electronics | Optional | 0.23-5 | ||
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2022-12-03 11:39:14 UTC | Superseded | Ubuntu Lunar amd64 | proposed | universe | electronics | Optional | 0.23-4 | ||
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2022-12-04 17:15:23 UTC | Superseded | Ubuntu Lunar amd64 | release | universe | electronics | Optional | 0.23-3 | ||
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2022-12-05 18:10:11 UTC | Deleted | Ubuntu Lunar amd64 | proposed | universe | electronics | Optional | 0.23-3 | ||
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2022-11-14 12:07:09 UTC | Superseded | Ubuntu Lunar amd64 | proposed | universe | electronics | Optional | 0.23-1 | ||
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2022-11-21 18:06:10 UTC | Superseded | Ubuntu Lunar amd64 | release | universe | electronics | Optional | 0.19-1 | ||
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