So I've scanned a bunch of machines and some have P_LVL2_LAT and P_LVL3_LAT defined as non supporting C2/C3 and the DSDT does not contain a _CST. Some newer CPUs such a Sandybridge are configured like this and the Intel idle driver figures out the number of C states from the CPU id rather than trusting the firmware provided data (be it existent or not).
So.. perhaps I could phrase the warning something like:
"FADT P_LVL2_LAT is 101, a value > 100 indicates that the C2 state is not defined in the FADT. C states either defined in the _CST object or determined by the kernel from the CPU id."
@Alex,
So I've scanned a bunch of machines and some have P_LVL2_LAT and P_LVL3_LAT defined as non supporting C2/C3 and the DSDT does not contain a _CST. Some newer CPUs such a Sandybridge are configured like this and the Intel idle driver figures out the number of C states from the CPU id rather than trusting the firmware provided data (be it existent or not).
So.. perhaps I could phrase the warning something like:
"FADT P_LVL2_LAT is 101, a value > 100 indicates that the C2 state is not defined in the FADT. C states either defined in the _CST object or determined by the kernel from the CPU id."