The cmp r2, r4; sbcs r1, r3, r5 sequence is from the *arm_cmpdi_insn
pattern.
This is a performance regression. It is exposed in the kernel as the
kernel doesn't have a implementation of __aeabi_lcmp, although it does
have __aeabi_ulcmp.
Changing the flags to -O2, -O3, or -mthumb doesn't work around the
problem. The issue does not exist in gcc-4.5.3, gcc-4.6.1,
gcc-linaro-4.6-2011.08, or upstream r178624.
I've set it to medium priority as it is a ftbfs and a performance
regression.
Thank you for the bug report. I've confirmed this with the gcc-linaro- 4.6-2011. 09 RC on ARM:
michaelh@ leo1:~/ linaro/ bugs$ /tools/ toolchains/ arch/armv7l/ gcc-linaro- 4.6-2011. 09-armv7l- natty-cbuild181 -ursa4- cortexa9r1/ bin/gcc -O2 -marm -S lp850099.c leo1:~/ linaro/ bugs$ cat lp850099.s
michaelh@
test:
stmfd sp!, {r3, r4, r5, lr}
rsbs r4, r0, #0
rsc r5, r1, #0
mov r3, r5
ldrd r0, [r2]
mov r2, r4
bl __aeabi_lcmp
cmp r0, #0
movgt r0, #0
movle r0, #1
ldmfd sp!, {r3, r4, r5, pc}
Due to the memory reference, the compiler generates a call to the 64
bit signed compare helper function. Previous versions inlined the
compare:
test:
stmfd sp!, {r4, r5}
ldrd r4, [r2]
rsbs r2, r0, #0
rsc r3, r1, #0
cmp r2, r4
sbcs r1, r3, r5
movlt r0, #0
movge r0, #1
ldmfd sp!, {r4, r5}
bx lr
The cmp r2, r4; sbcs r1, r3, r5 sequence is from the *arm_cmpdi_insn
pattern.
This is a performance regression. It is exposed in the kernel as the
kernel doesn't have a implementation of __aeabi_lcmp, although it does
have __aeabi_ulcmp.
Changing the flags to -O2, -O3, or -mthumb doesn't work around the 4.6-2011. 08, or upstream r178624.
problem. The issue does not exist in gcc-4.5.3, gcc-4.6.1,
gcc-linaro-
I've set it to medium priority as it is a ftbfs and a performance
regression.