TCE

FPU_SP_MUL FU's pipeline is not stalled when glock = '1'

Bug #942551 reported by Zhang Xin-Johnson on 2012-02-28

This bug affects 1 person

Affects		Status	Importance	Assigned to	Milestone
	TCE	Fix Released	High	Timo Viitanen

Bug Description

In share/tce/hdb/fpu_embedded_vhdl/fpu_sp_mul.vhdl (tce-1.5):

    MUL_REGS: process(clk, rstx)
    begin
      if rstx = '0' then
                ……
      elsif clk'event and clk='1' then
        if True then
                ……
        end if;
      end if;
    end process;

Related branches

lp:tce/1.5

Revision history for this message

Pekka Jääskeläinen (pekka-jaaskelainen) wrote on 2012-02-28:

Can you try to fix this and send us a patch? It should be simple if you imitate how it's done in other FUs for which the glock works? The author of these FUs is coming back to work in April.

Changed in tce:
importance:	Undecided → High

Revision history for this message

Zhang Xin-Johnson (johnson-zhang) wrote on 2012-02-28:

To my understanding, it can be solved by simply changing the "True" to "glock = '0'". However, I have no idea if it's a real bug or the author wrote it intentionally.

Pekka Jääskeläinen (pekka-jaaskelainen) on 2012-02-28